A certain type of wiring substrate known in the art includes a core layer, a first insulating layer formed at one surface of the core layer, a second insulating layer laminated on the first insulating layer, a third insulating layer formed at the other surface of the core layer, and a solder resist layer laminated on the third insulating layer. Each of the first insulating layer and the second insulating layer includes a plurality of insulating films. The first insulating layer further includes a first wiring layer formed therein. The surface of the first wiring layer on which the second insulating layer is laminated has a second wiring layer formed thereon. The first insulating layer and the third insulating layer are made of thermosetting resin. The second insulating layer and the solder resist layer are made of photosensitive resin. The first insulating layer has a first via interconnection embedded therein, and the second insulating layer has a second via interconnection embedded therein. One end face of the first via interconnection embedded in the first insulating layer is exposed at the uppermost layer of the first insulating layer on which the second insulating layer is laminated. This end face is directly bonded with the second wiring layer. The surface of the first insulating layer on which the second insulating layer is laminated is a polished surface. The second wiring layer has a higher wiring density than the first wiring layer (see Patent Document 1, for example).
The wiring substrate disclosed in Patent Document 1 has the second wiring layer formed on the first insulating layer that includes the first wiring layer and the first via interconnection embedded therein.
This arrangement makes it difficult to reduce the thickness of the wiring substrate disclosed in Patent Document 1.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2014225632